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PATHHardware Documentation > PowerBook G3 Series 1999

Backside Cache

The controller and the tag storage for the backside cache are built into the microprocessor chip. The cache controller includes bus management and control hardware that allows the cache to run at an independent sub-multiple of the processor's clock speed, rather than at the slower clock speed of the main system bus. In the new PowerBook G3 Series computer, the ratio of the microprocessor and backside cache clock speeds is 5:2.

The data storage for the backside L2 cache consists of either 512 KB or 1 MB of fast static RAM on the processor module.


© 1999 Apple Computer, Inc. – (Last Updated 29 April 99)